1. Field of the Invention
The present invention relates to a semiconductor device containing an internal voltage generating circuit for generating an internal voltage, and more particularly to an internal voltage generating circuit capable of stably generating an internal voltage in accordance with an external power supply voltage even for specifications of a plurality of external power supply voltages and a plurality of interfaces.
2. Description of the Background Art
FIG. 36 is a diagram schematically showing the configuration of an array portion of a conventional dynamic random access memory (DRAM). In FIG. 36, a memory cell MC is disposed at an intersection of bit lines BL and ZBL and a word line WL. In FIG. 36, memory cell MC disposed at the intersection of the bit line BL and word line WL is representatively shown.
Generally, in a memory array, memory cells MC are disposed in rows and columns, and word line WL is disposed corresponding to each memory cell row. For each memory cell column, a pair of bit lines BL and ZBL is disposed. A memory cell is disposed at the intersection of one of paired bit lines and a word line. Complementary data are transferred through bit lines BL and ZBL.
Memory cell MC includes a memory capacitor MQ for storing information in the form of electric charges and an access transistor MT for coupling memory cell capacitor MQ to a corresponding bit line BL (or ZBL) in accordance with a signal voltage on word line WL. Access transistor MT is usually formed of an N-channel MOS transistor (insulated gate field effect transistor), and a negative bias voltage Vbb is applied to a back gate of access transistor MT. By applying negative bias voltage Vbb to the back gate of access transistor MT, stabilization of the threshold voltage of access transistor MT, reduction in parasitic capacitance between a signal line and a substrate region, and reduction in junction capacitance of the drain and source of access transistor MT are intended to achieve.
Bit lines BL and ZBL are provided with a bit line equalizing circuit BPE for precharging and equalizing bit lines BL and ZBL to a bit line precharge voltage Vb1 level in a standby state, and a sense amplifier SA for differentially amplifying and latching the voltages on bit lines BL and ZBL.
Sense amplifier SA is provided with: a sense amplifier activating transistor ASPT that is made conductive, when a sense amplifier activate signal/SAP is activated, to couple a high-level power supply node of sense amplifier SA to a sense power supply line for transmitting an array power supply voltage Vdds; and a sense amplifier activating transistor ASNT that is made conductive, when a sense amplifier activate signal SAN is activated, to couple a low-level power supply node of sense amplifier SA to a sense ground line for transmitting a ground voltage Vss.
Bit line equalizing circuit BPE transmits bit line precharge voltage Vb1 of an intermediate voltage (Vdds/2) of array power supply voltage Vdds to bit lines BL and ZBL in accordance with a bit line equalize instruction signal BLEQ.
When selected, word line WL is driven to a high voltage Vpp level higher than array power supply voltage Vdds. By driving selected word line WL to high voltage Vpp level, without a threshold voltage loss across access transistor MT of memory cell MC, H data of array power supply voltage Vdds level is stored in a storage node of memory capacitor MQ.
Memory capacitor MQ receives a predetermined cell plate voltage Vcp at an electrode node (cell plate node) facing the storage node storing data. Usually, cell plate voltage Vcp is at the voltage level of intermediate voltage (Vdds/2) of array power supply voltage Vdds, similarly to bit line precharge voltage Vb1.
As described above, in a DRAM, a plurality of kinds of voltages of different voltage levels are used. In the case of generating the plurality of kinds of voltages externally for application to a DRAM, the scale of a system is increased and, due to loss on external wires, current consumption of the whole system also increases. In the DRAM as well, since the number of power supply pin terminals increases, the size of the package becomes large. Therefore, generally, the plurality of kinds of voltages are generated within a DRAM.
FIG. 37 is a diagram schematically showing the configuration of a portion related to internal voltages of the DRAM. In FIG. 37, the DRAM includes: a memory cell array 902 having a plurality of memory cells (memory cell MC in FIG. 36) arranged in rows and columns; a control circuit 904 for generating an operation control signal for implementing an operation mode designated by a command CMD in accordance with command CMD externally applied; a row selecting circuit 906 which is activated under control of control circuit 904 to drive a word line disposed corresponding to an addressed row in memory cell array 902 in accordance with a row address signal RA externally applied; a sense amplifier group 908 which is selectively activated by control circuit 904 to sense, amplify, and latch data of a memory cell on a row selected by row selecting circuit 906; a column selecting circuit 910 which operates under control of control circuit 904 and, when activated, selects a memory cell corresponding to an addressed column in memory cell array 902 in accordance with a column address signal CA externally applied; and an internal voltage generating circuit 900 for generating various internal voltages Vpp, Vbb, Vbl, Vcp, Vdds, and Vddp in accordance with an external power supply voltage EXVDD.
A peripheral power supply voltage Vddp from internal voltage generating circuit 900 is applied to control circuit 904 and row selecting circuit 906. A high voltage Vpp from internal voltage generating circuit 900 is also applied to row selecting circuit 906.
In row selecting circuit 906, a row selection signal is generated by a row decoding circuit which receives peripheral power supply voltage Vddp as an operation power supply voltage and, according to the row selection signal, a word line selection signal at high voltage Vpp level is transmitted by a word driver to a word line disposed corresponding to the selected row.
To memory cell array 902, bit line precharge voltage Vb1, cell plate voltage Vcp, and negative bias voltage Vbb supplied to a substrate region of memory cell array 902 are applied. To sense amplifier group 908, array power supply voltage Vdds is applied as an operation power supply voltage via the sense power supply line.
To column selecting circuit 910, usually, peripheral power supply voltage Vddp is applied as an operation power supply voltage. However, a column selection signal output from column selecting circuit 910 may be at the array power supply voltage Vdds level. Usually, peripheral power supply voltage Vddp is at a voltage level higher than array power supply voltage Vdds.
By causing peripheral circuits such as control circuit 904 to operate with peripheral power supply voltage Vddp and causing sense amplifier group 908 associated with memory cell array 902 to operate in accordance with array power supply voltage Vdds, the peripheral circuits are operated at high speed to achieve high-speed access, and the dielectric breakdown of the access transistor and memory cell capacitor of a memory cell is secured to store data stably.
In a semiconductor device, as the system scale increases, to prevent heat generation and the like, low power consumption is more strongly required. Particularly, in applications of portable equipment using a battery as a power source, current consumption has to be reduced from the viewpoint of battery's life as well. Particularly, as to a standby state in which no data access is performed, the time period of the standby state is longer than the time period in which a data processing is actually performed. A DRAM is required, in the standby state, only to hold data, and reduction in current consumption in the standby state is strongly required.
As a method of reducing current consumption in such a standby state, an operation mode called a power down mode is used. In the power down mode, supply of the operation power supply voltage is stopped in the circuitry not related to data retention such as an address input buffer circuit. By cutting off a DC (direct current) path of the circuitry that is non-related to data retention, a leakage current of the circuitry is reduced, and current consumption is reduced.
In uses of portable equipment and the like, recently, reduction in standby power is further demanded. To accommodate for such demand of a very low standby current, a mode called a “deep power down mode” is used. In the deep power down mode, an internal voltage generating operation of internal voltage generating circuit 900 is stopped. Since the power down mode is set by an external command, a power supply voltage is applied to circuitry related to release of the power down mode such as a command decoder receiving command CMD.
When the deep power down mode instruction is applied, as shown in FIG. 37, a power cut signal PCUT is generated from control circuit 904. Power cut signal PCUT is at the level of peripheral power supply voltage Vddp. In order to stop the operation of the circuitry for generating an internal voltage from external power supply voltage EXVDD, by a level converting circuit 915, power cut signal PCUT is converted to a power cut enable signal PCUTe having an amplitude of the external power supply voltage EXVDD level. Power cut enable signal PCUTe is supplied to the peripheral circuits such as row selecting circuit 906 and column selecting circuit 910 and the current path of each of the peripheral circuits is cut off.
Power cut enable signal PCUTe is applied to the circuit portion other than a circuit for controlling an operation related to the deep power down mode also in control circuit 904, and the current path of the circuit portion is cut off.
In the deep power down mode, current is consumed by only the necessary circuitry and the current path of unnecessary circuitry is cut off, thereby preventing occurrence of leakage current to reduce current consumption greatly.
A DRAM is used in various systems. In the systems, various power supply voltages exist. For example, as external power supply voltage EXVDD, 3.3V and 2.5V exist. As interfaces, not only an LVTTL, there is a 1.8VIO interface. In the 1.8VIO interface, although the external power supply voltage is 2.5V or 3.3V, the amplitude of an input signal is set to 1.8V. VIH and VIL are set to, for example, 0.8VDDQ and 0.2VDDQ on the basis of an output power supply voltage VDDQ.
In a DRAM, in the case where an internal voltage is generated from a different external power supply voltage with the same circuit configuration, since an operation condition of the internal voltage generating circuit vary according to the external power supply voltage level, such a problem occurs that the internal voltage at an optimum voltage level cannot be efficiently generated.
In the case of designing an internal voltage generating circuit in accordance with each external power supply voltage level or interface specification, to be simply adapted to the voltage level of an external power supply voltage, a plurality of kinds of chips, the same in configuration of main internal circuitry but different in configuration of the internal voltage generating circuit, have to be fabricated. It results in problems that the manufacturing efficiency deteriorates and the cost increases.
Therefore, from the viewpoints of product management and cost, it is preferable to implement an internal voltage generating circuit adapted to an external power supply voltage level or interface specification by use of mask interconnection or fixing of a voltage at a bonding pad in a slice process while manufacturing a common circuit part for a plurality of kinds external power supply voltages and interfaces in a master process.